नम्र प्रोसेसर

नम्र प्रोसेसर (soft processor या soft microprocessor या softcore microprocessor) उस माइक्रोप्रोसेसर कोर को कहते हैं जिसको किसी एफपीजीए, सीपीएलडी या एसिक में ढाला जा सके।

नम्र कोरों की तुलना

प्रोसेसर	विकासकर्ता	मुक्तस्रोत	बस सपोर्ट	टिप्पणियाँ	परियोजना गृह	वर्णन की भाषा
अम्बर (प्रोसेसर)	कोनोर सैन्टिफोर्ट	LGPLv2.1	Wishbone	ARMv2a 3-stage or 5-stage pipeline	Project page at Opencores	Verilog
BERI	University of Cambridge	BSD		एमआईपीएस	Project page	Bluespec
Dossmatik	René Doss	CC BY-NC 3.0, except commercial applicants have to pay a licence fee.	Pipelined bus	MIPS I instruction set pipeline stages	Dossmatik	VHDL
NEO430	Stephan Nolting	हाँ	Wishbone (Avalon, AXI4-Lite)	16-bit MSP430 ISA-compatible, very small size, many peripherals, highly customizable	NEO430	VHDL
MCL65	MicroCore Labs	हाँ	Ultra-small-footprint microsequencer-based 6502 core	252 Spartan-7 LUTs. Clock cycle-exact.	MCL65 Core
MCL51	MicroCore Labs	नहीं	Ultra-small-footprint microsequencer-based 8051 core	312 Artix-7 LUTs. Quad-core 8051 version is 1227 LUTs.	MCL51 Core
MCL86	MicroCore Labs	नहीं	8088 BIU provided. Others easy to create.	Cycle accurate 8088/8086 implemented with a microsequencer. Less than 2% utilization of Kintex-7.	MCL86 Core
TSK3000A	Altium	Royalty-free	Wishbone	32-bit R3000-style RISC modified Harvard-architecture CPU	Embedded Design on Altium Wiki
TSK51/52	Altium	Royalty-free	Wishbone / Intel 8051	8-bit Intel 8051 instruction set compatible, lower clock cycle alternative	Embedded Design on Altium Wiki
OpenSPARC T1	Sun	हाँ		64-bit	OpenSPARC.net	Verilog
MicroBlaze	Xilinx	नहीं	PLB, OPB, FSL, LMB, AXI4		Xilinx MicroBlaze
PicoBlaze	Xilinx	नहीं			Xilinx PicoBlaze	VHDL, Verilog
Nios, Nios II	Altera	नहीं	Avalon		Altera Nios II	Verilog
Cortex-M1	ARM	नहीं	[1]	70–200  MHz, 32-bit RISC	[2]	Verilog
eSi-RISC	EnSilica	नहीं	AMBA AXI, AHB and APB	Configurable as 16- or 32-bit. Supports ASIC and FPGA.	EnSilica eSi-RISC	Verilog
LatticeMico8	Lattice	हाँ	Wishbone		LatticeMico8	Verilog
LatticeMico32	Lattice	हाँ	Wishbone		LatticeMico32	Verilog
LEON2(-FT)	ESA	हाँ	AMBA2	SPARC V8	ESA	VHDL
LEON3/4	Aeroflex Gaisler	हाँ	AMBA2	SPARC V8	Aeroflex Gaisler	VHDL
Tacus/PIPE5	TemLib	हाँ	Pipelined bus	SPARC V8	TEMLIB	VHDL
Navré	Sébastien Bourdeauducq	हाँ	Direct SRAM	Atmel AVR compatible 8-bit RISC	Project page at Opencores	Verilog
OpenRISC	OpenCores	हाँ	Wishbone	32-bit; done in ASIC, Actel, Altera, Xilinx FPGA.	OR1K	Verilog
ARC	ARC International, Synopsys	नहीं		16/32-bit ISA RISC	DesignWare ARC	Verilog
pAVR	Doru Cuturela	हाँ		Atmel AVR-compatible 8-bit RISC	Project page at Opencores	VHDL
AEMB	Shawn Tan	हाँ	Wishbone	MicroBlaze EDK 3.2 compatible	AEMB	Verilog
OpenFire	Virginia Tech CCM Lab	हाँ	OPB, FSL	Binary compatible with the MicroBlaze	[3]	Verilog
SecretBlaze	LIRMM, University of Montpellier / CNRS	हाँ	Wishbone	MicroBlaze ISA, VHDL	SecretBlaze	VHDL
SpartanMC	TU Darmstadt / TU Dresden	हाँ	Custom (AXI support in development)	18-bit ISA (GNU Binutils / GCC support in development)	SpartanMC	Verilog
SYNPIC12	Miguel Angel Ajo Pelayo	MIT		PIC12F compatible, program synthesised in gates	nbee.es	VHDL
PacoBlaze	Pablo Bleyer	हाँ		Compatible with the PicoBlaze processors	PacoBlaze	Verilog
CPU86	HT-Lab	हाँ		8088-compatible CPU in VHDL	cpu86	VHDL
xr16	Jan Gray	नहीं	XSOC abstract bus	16-bit RISC CPU and SoC featured in Circuit Cellar Magazine #116-118	XSOC/xr16	Schematic
JOP	Martin Schoeberl	हाँ	SimpCon / Wishbone (extension)	Stack-oriented, hard real-time support, executing Java bytecode directly	Jop	VHDL
ERIC5	Entner Electronics	नहीं		9-bit RISC, very small size, C-programmable	ERIC5	VHDL
YASEP	Yann Guidon	AGPLv3	Direct SRAM	16 or 32 bits, RTL in VHDL & asm in JS, microcontroller subset : ready	yasep.org (Firefox required)	VHDL
Zet	Zeus Gómez Marmolejo	हाँ	Wishbone	x86 PC clone	Zet	Verilog
f32c	University of Zagreb	BSD	AXI, SDRAM, SRAM	32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain	f32c	VHDL
ZipCPU	Gisselquist Technology	GPLv3	Wishbone, B4/pipelined	32-bit CPU targeted for minimal FPGA resource usage	zipcpu.com	Verilog
ZPU	Zylin AS	हाँ	Wishbone	Stack based CPU, configurable 16/32 bit datapath, eCos support	Zylin CPU	VHDL
ZPUino	Álvaro Lopes	हाँ	Wishbone	Zylin's ZPU based SoC, 32 bit, Linux support.	ZPUino	VHDL
OpenPiton	Princeton Parallel Group	हाँ		Manycore SPARC V9	OpenPiton	Verilog
s80x86	Jamie Iles	GPLv3	Custom	80186-compatible GPLv3 core	s80x86	SystemVerilog
VexRiscv	SpinalHDL	हाँ	AXI4 / Avalon	32-bit, RISC-V, up to 340  MHz on Artix 7. Up to 1.44  DMIPS/MHz.	https://web.archive.org/web/20190417072643/https://github.com/SpinalHDL/VexRiscv	VHDLVerilog (SpinalHDL)

इन्हें भी देखें

• System-on-a-chip (SoC)
• Field-programmable gate array (FPGA)
• Reconfigurable computing
• VHDL
• Verilog

बाहरी कड़ियाँ

• Soft CPU Cores for FPGA
• Detailed Comparison of 12 Soft Microprocessors
• FPGA CPU News
• Freedom CPU website
• Microprocessor cores on Opencores.org (Expand the "Processor" tab)
• NikTech 32 bit RISC Microprocessor MANIK.